1. Field of the Invention
The present invention relates generally to gate dielectrics for integrated circuit transistors. More particularly, the invention relates to processes and structures for optimizing the thickness of gate dielectrics.
2. Description of the Related Technology
In the field of integrated circuit fabrication, current leakage through thin dielectric layers presents a continuing challenge to device integration. Leakage through gate dielectrics of field effect transistors (FETs) is known as Fowler-Nordheim currents, while gate induced diode leakage (GIDL) occurs at the edge of the gate electrode. As the gate dielectrics, which are typically formed of silicon oxide, become increasingly thinner due to continued scaling of integrated circuits in pursuit of faster and more efficient circuit operation, GIDL occurs even during transistor off states.
Certain integrated devices, such as transistors within memory arrays of a dynamic random access memory (DRAM), are particularly sensitive to GIDL. Moreover, significant transistor GIDL can induce leakage at storage nodes of a memory array. Accordingly, gate oxides in memory arrays must be effective at resisting GIDL for proper operation.
Transistors leakage tends to occur at gate edges, where electric fields are concentrated. Accordingly, one partial solution to the problem of GIDL, where conventional oxides are used for the gate dielectric, is to perform a re-oxidation process. The re-oxidation is performed after forming gate electrodes, such that the gate oxide edges under the gate electrode corners are thickened relative to the remainder of the gate oxide dielectric. However, metals used in word lines (part of which form the gate electrodes) are susceptible to degradation during the re-oxidation process. Recently popular word line materials, such as tungsten, are particularly susceptible to oxidation.
Peripheral circuits of a DRAM chip generally include logic circuits, such as address decoders and read/write control circuits. These logic circuits in the periphery of the memory chip, in contrast to memory array transistor, require faster transistor switching times. Such aggressive operation is facilitated by thinner gate oxides in these peripheral circuits. Logic circuits also tolerate a higher GIDL current, as compared to memory arrays, such that thinning gate oxides within the peripheral areas may be feasible from a GIDL standpoint.
In order to accommodate the differing needs of the memory array and peripheral circuits, the circuit design can include two or more different thicknesses of gate oxide on the same silicon substrate. According to the prior art, different thicknesses of gate oxide have been formed by selective oxidation through an existing thin oxide layer (in areas which require thick oxides), or by selective etching of an existing oxide layer (in areas which require thinner oxides). Either selective oxidation or etching, require at least one additional mask, which increases the cost of fabrication.
Moreover, thin gate oxides in field effect transistors are more easily worn out due to the injection of hot electrical carriers through the channel which is formed below the thin oxide. Such oxide wear out may reduce reliability, yield and/or life span of the device.
Therefore, a need exists for processes and structures which address the various needs of memory arrays and logic circuits.